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Preliminary Technical Data
FEATURES
High Speed Isolated RS-485 Transceiver with Integrated Transformer Driver ADM2485
GENERAL DESCRIPTION
The ADM2485 differential bus transceiver is an integrated, galvanically isolated component designed for bidirectional data communication on multipoint bus transmission lines. It is designed for balanced transmission lines and complies with ANSI TIA/EIA RS-485-A-1998 and ISO 8482:1987(E). The device employs Analog Devices' iCoupler technology to combine a 3-channel isolator, a 3-state differential line driver, and a differential input receiver into a single package. An onchip oscillator outputs a pair of square waveforms which drive an external transformer to provide isolated power with an external transformer. The logic side of the device can be powered with either a 5 V or a 3 V supply while the bus side is powered with an isolated 5 V supply. The ADM2485 driver has an active high enable. The driver differential outputs and the receiver differential inputs are connected internally to form a differential input/output port that imposes minimal loading on the bus when the driver is disabled or when VDD1 or VDD2 = 0 V. Also provided is an active high receiver disable that causes the receive output to enter a high impedance state. The device has current-limiting and thermal shutdown features to protect against output short circuits and situations where bus contention might cause excessive power dissipation. The part is fully specified over the industrial temperature range and is available in a 16-lead wide-body SOIC package.
Half-duplex isolated RS-485 transceiver Integrated oscillator driver for external transformer PROFIBUS compliant Complies with ANSI TIA/EIA RS-485-A-1998 and ISO 8482:1987(E) 16 Mbps data rate 5 V or 3 V operation (VDD1) 50 nodes on bus Receiver open-circuit, fail-safe design High common-mode transient immunity: >25 kV/s Isolated DE OUT status output Thermal shutdown protection Safety and regulatory approvals (pending): UL recognition--2500 VRMS for 1 minute per UL 1577 CSA component acceptance notice #5A VDE certificate of conformity DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01 DIN EN 60950 (VDE 0805):2001-12; EN 60950: 2000 VIORM = 560 V peak Operating temperature range: -40 to 85C Wide body 16-lead SOIC package
APPLICATIONS
Isolated RS-485/RS-422 interfaces PROFIBUS networks Industrial field networks Multipoint data transmission systems

FUNCTIONAL BLOCK DIAGRAM

Figure 1 Rev.PrK
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ADM2485 SPECIFICATIONS
2.7 VDD1 5.5 V, 4.75 V VDD2 5.25 V, TA = TMIN to TMAX, unless otherwise noted. Table 1.
Parameter DRIVER Differential Outputs Differential Output Voltage, VOD Min Typ Max
Preliminary Technical Data
Unit
Test Conditions/Comments
2.1 2.1 2.1 |VOD| for Complementary Output States Common-Mode Output Voltage, VOC |VOC| for Complementary Output States Output Short-Circuit Current, VOUT = High Output Short-Circuit Current, VOUT = Low Bus Enable Output Output High Voltage
5 5 5 5 0.2 3 0.2 200 200
V V V V V V V mA mA V V V V V V V V A
R = , Figure 3 R = 50 (RS-422), Figure 3 R = 27 (RS-485), Figure 3 VTST = -7 V to 12 V, VDD1 4.75, Figure 4 R = 27 or 50 , Figure 3 R = 27 or 50 , Figure 3 R = 27 or 50 , Figure 3 -7 V VOUT +12 V -7 V VOUT + 12 V IODE = 20 A IODE = 1.6 mA IODE = 4 mA IODE = -20 A IODE = -1.6 mA IODE = -4 mA TxD, RTS, RE TxD, RTS, RE TxD, RTS, RE = VDD1 or 0 V
60 60 VDD2-0.1 VDD2-0.3 VDD2-0.4
VDD2-0.1 VDD2-0.2 0.1 0.2 0.1 0.3 0.4
Output Low Voltage
Logic Inputs Input High Voltage Input Low Voltage CMOS Logic Input Current (TxD, RTS, RE) RECEIVER Differential Inputs Differential Input Threshold Voltage, VTH Input Hysteresis Input Resistance (A, B) Input Current (A, B) RxD Logic Output: Output High Voltage Output Low Voltage
0.7 VDD1 -10 0.01 0.25 VDD1 10
-200 20 70 30
200
mV mV k mA mA V V V V mA A kHz V
0.6 -0.35 VDD1-0.1 VDD1-0.4
-7 V VCM +12V -7 V VCM +12V -7 V VCM +12V VIN = +12 V VIN = -7 V IOUT = 20 A, VA-VB=0.2 V IOUT = 4 mA, VA-VB=0.2 V IOUT = -20 A, VA-VB=-0.2 V IOUT = -4 mA, VA-VB=-0.2 V VOUT = GND or VCC 0.4 V VOUT 2.4 V
VDD1-0.2 0.2 0.1 0.4 85 1
Output Short Circuit Current Three-State Output Leakage Current Transformer Driver Oscillator Frequency Switch On resistance Start-Up Voltage
7
500 0.5 2.2
1.5 2.5
Rev. PrK | Page 2 of 15
Preliminary Technical Data
Parameter POWER SUPPLY CURRENT Logic Side Min Typ Max 1.3 1.0 4.0 0.8 1.1 2.1 Bus Side 43.0 58.0 COMMON-MODE TRANSIENT IMMUNITY1 HIGH FREQUENCY COMMON-MODE NOISE IMMUNITY 25 100 3.0 Unit mA mA mA mA mA mA mA mA mA kV/s mV
ADM2485
Test Conditions/Comments RTS = 0 V, VDD1 = 5.5 V 2 Mbps, VDD1 = 5.5 V, Figure 5 16 Mbps, VDD1 = 5.5 V, Figure 5 RTS = 0 V, VDD1 = 3 V 2 Mbps, VDD1 = 3 V, Figure 5 16 Mbps, VDD1 = 3 V, Figure 5 RTS = 0 V 2 Mbps, RTS = VDD1, Figure 5 16 Mbps, RTS = VDD1, Figure 5 VCM = 1 kV, Transient Magnitude = 800 V VHF = +5V, -2 V < VTEST2 < 7 V, 1 < fTEST < 50 MHz, Figure 6
1
CM is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation. VCM is the common-mode potential difference between the logic and bus sides. The transient magnitude is the range over which the common-mode is slewed. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
TIMING SPECIFICATIONS
2.7 VDD1 5.5 V, 4.75 V VDD2 5.25 V, TA = TMIN to TMAX, unless otherwise noted. Table 2.
Parameter DRIVER Maximum Data Rate Propagation Delay Input to Output tPLH, tPHL RTS-to-DE Propagation Delay Driver O/P to O/P tSKEW Rise/Fall Time tR, tF Enable Time Disable Time Enable Skew, |tAZH-tBZL|, |tAZL-tBZH| Disable Skew, |tAHZ-tBLZ|, |tALZ-tBHZ| RECEIVER Propagation Delay tPLH, tPHL Differential Skew tSKEW Enable Time Disable Time Min 16 25 20 Typ Max Unit Mbps ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions/Comments
45 35 2 5 43 43 1 2
55 55 5 15 53 55 3 5 55 5 13 13
RLDIFF = 54 , CL1 = CL2 = 100 pF; See Figure 7. See Figure 8. RLDIFF = 54 , CL1 = CL2 = 100 pF; See Figure 7 and Figure 12. RLDIFF = 54 , CL1 = CL2 = 100 pF; See Figure 7 and Figure 12. See Figure 9 and Figure 14. See Figure 9 and Figure 14. See Figure 9 and Figure 14. See Figure 9 and Figure 14. CL = 15 pF; See Figure 10 and Figure 13. CL = 15 pF; See Figure 10 and Figure 13. RL = 1 k, CL = 15 pF; See Figure 11 and Figure 15. RL = 1 k, CL = 15 pF; See Figure 11 and Figure 15.
25
45 3 3
Rev. PrK | Page 3 of 15
ADM2485 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. All voltages are relative to their respective ground. Table 3.
Parameter VDD1 VDD2 Digital Input Voltage (RTS, RE, TxD) Digital Output Voltage RxD DE OUT D1, D2 Driver Output/Receiver Input Voltage Operating Temperature Range Storage Temperature Range Average Output Current per Pin JA Thermal Impedance Lead Temperature Soldering (10 sec) Vapour Phase (60 sec) Infrared (15 sec) Rating -0.5 V to +6 V -0.5 V to +6 V -0.5 V to VDD1 + 0.5 V -0.5 V to VDD1 + 0.5 V -0.5 V to VDD2 + 0.5 V 13V -9 V to +14 V -40C to +85C -55C to +150C -35 mA to +35 mA 73C/W 300C 215C 220C
Preliminary Technical Data
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrK | Page 4 of 15
Preliminary Technical Data ADM2485E CHARACTERISTICS
PACKAGE CHARACTERISTICS
Table 2.
Parameter Resistance (Input-Output)1 Capacitance (Input-Output)1 Input Capacitance2 Input IC Junction-to-Case Thermal Resistance Output IC Junction-to-Case Thermal Resistance Symbol RI-O CI-O CI JCI JCO Min Typ 1012 3 4 33 28 Max Unit pF pF C/W C/W Test Conditions f = 1 MHz
ADM2485
Thermocouple located at center of package underside
1 2
Device considered a two-terminal device: Pins 1, 2, 3, 4, 5, 6, 7, and 8 shorted together, and Pins 9, 10, 11, 12, 13, 14, 15, and 16 shorted together. Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADM2485 is to be approved by the following organizations: Table 3.
Organization UL Approval Type To be recognized under 1577 component recognition program. Notes In accordance with UL1577, each ADM2485 is proof-tested by applying an insulation test voltage 3000 V rms for 1 second (current leakage detection limit = 5 A). In accordance with VDE 0884, each ADM2485 is proof-tested by applying an insulation test voltage 1050 VPEAK for 1 second (partial discharge detection limit = 5 pC).
CSA VDE
To be approved under CSA Component Acceptance Notice #5A. To be certified according to DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 4.
Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group Symbol L(I01) L(I02) Value 2500 5.15 min 5.5 min 0.017 min >175 IIIa Unit V rms mm mm mm V Conditions 1-minute duration. Measured from input terminals to output terminals, shortest distance through air. Measured from input terminals to output terminals, shortest distance along body. Insulation distance through insulation. DIN IEC 112/VDE 0303 Part 1. Material Group (DIN VDE 0110, 1/89,).
CTI
Rev. PrK | Page 5 of 15
ADM2485
VDE 0884 INSULATION CHARACTERISTICS
Preliminary Technical Data
This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data must be ensured by means of protective circuits. An asterisk (*) on packages denotes VDE 0884 approval for 560 V peak working voltage. Table 5.
Description Installation classification per DIN VDE 0110 for rated mains voltage 150 V rms 300 V rms 400 V rms Climatic classification Pollution degree (DIN VDE 0110, Table 1) Maximum working insulation voltage Input to output test voltage, Method b1 VIORM x 1.875 = VPR, 100% production tested, tm = 1 sec, partial discharge < 5 pC Input to output test voltage, Method a (After environmental tests, Subgroup 1) VIORM x 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC (After input and/or safety test, Subgroup 2/3) VIORM x 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC Highest allowable overvoltage (Transient overvoltage, tTR = 10 sec) Safety-limiting values (maximum value allowed in the event of a failure. See thermal derating curve) Case temperature Input current Output current Insulation resistance at Ts, VIO = 500 V Symbol Characteristic I to IV I to III I to II 40/85/21 2 560 1050 Unit
VIORM VPR
VPEAK VPEAK
896 VPR VTR 672 4000
VPEAK VPEAK VPEAK
TS IS, INPUT IS, OUTPUT Rs
150 265 335 >109
C mA mA
Rev. PrK | Page 6 of 15
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
D1 1 D2 2 GND1 3 VDD1 4 RxD 5 RE 6 RTS 7 TxD 8
16 VDD2 15 GND2
ADM2485
ADM2485
T OP V IEW
( Not t o Scale)
14 GND2 13 B 12 A 11 GND2 10 DE OUT 9
GND2
Figure 2. Pin Configuration
Table 4.
Pin 1 2 3 4 5 6 7 8 10 12 13 9,11,14,15 16 Mnemonic D1 D2 GND1 VDD1 RxD RE RTS TxD DE OUT A B GND2 VDD2 Function Transformer driver terminal 1. Transformer driver terminal 2. Ground, Logic Side. Power Supply Logic Side, 3V or 5V. Decoupling capacitor to GND1 required, capacitor value should be between 0.01 F and 0.1 F. Receiver Output data. This output is high when (A - B) > 200 mV, and low when (A - B) < -200 mV. The output is tri-stated when the receiver is disabled, i.e. when RE is driven high. Receiver Enable input. This is an active-low input. Driving this input low enables the receiver, while driving it high disables the receiver. Driver enable input. Driving this input high enables the driver, while driving it low disables the driver. Driver input. Data to be transmitted by the driver is applied to this input. Driver Enable status output Noninverting Driver Output/Receiver Input. When the driver is disabled or VDD1 or VDD2 is powered down, pin A is put in a high impedance state to avoid overloading the bus. Inverting Driver Output/Receiver Input. When the driver is disabled or VDD1 or VDD2 is powered down, pin B is put in a high impedance state to avoid overloading the bus. Ground, Bus Side. Power Supply Bus Side, Isolated 5V supply. Decoupling capacitor to GND2 required, capacitor value should be between 0.01 F and 0.1 F.
Rev. PrK | Page 7 of 15
ADM2485 TEST CIRCUITS
R VOD R
04604-005
Preliminary Technical Data
A RLDIFF
VOC
CL1 CL2
04736-005
B
Figure 3. Driver Voltage Measurement
Figure 7. Driver Propagation Delay
375
DE 150
VOD3 60 VTST
04604-006
RTS
GALVANIC ISOLATION
DE OUT
50pF
375
TxD
Figure 4. Driver Voltage Measurement
RxD RE
A B
DE OUT DE
GALVANIC ISOLATION
150
04604-008
RTS
VDD1
GND1
VDD2
GND2
TxD
VDD2 A B 195
Figure 8. RTS to DE OUT Propagation Delay
VCC A 110 S1 B
04604-004
RxD RE VDD1 GND1
110 195 GND2
TxD
S2
04604-009
50pF
VOUT
VDD2
GND2
RTS
Figure 5. Supply-Current Measurement Test Circuit
A
Figure 9. Driver Enable/Disable
RTS
GALVANIC ISOLATION
DE DE OUT
B
RE
VOUT
04604-012
CL
TxD
VDD2 195 B A 110 470nF 195 GND2 50 22k 50 FTEST, 110nF VHF
Figure 10. Receiver Propagation Delay
VCM(HF)
RxD
2.2k RECEIVE GND2 ENABLE VDD1 100nF
+1.5V S1
04604-010
VCC RL RE CL VOUT
GND1
VDD2 100nF
GND2
VTEST2
-1.5V
S2
04604-013
Figure 6. High Frequency Common-Mode Noise Test Circuit
RE IN
Figure 11. Receiver Enable/Disable
Rev. PrK | Page 8 of 15
Preliminary Technical Data SWITCHING CHARACTERISTICS
3V 1.5V 0V 1.5V
ADM2485
0.7VDD1 RTS 0.5VDD1 0.5VDD1 0.3VDD1
tPLH
B 1/2VO VO A
tPHL
tZL
tLZ
A-B
2.3V
VOH +0.5V
tSKEW = |tPLH - tPHL|
90% POINT
tZH
2.3V
tHZ
VOH -0.5V
VOL VOH
VO 0V -VO
90% POINT
A-B
0V
10% POINT 10% POINT
02603-009
tR
tF
Figure 12. Driver Propagation Delay, Rise/Fall Timing
Figure 14. Driver Enable/Disable Timing
0.7VDD1
A-B 0V 0V
RE
0.5VDD1
0.5VDD1 0.3VDD1
tPLH
tZL
tPHL VOH
RxD 1.5V O/P LOW
tLZ
VOH +0.5V VOL
RxD
1.5V
tSKEW = |tPLH - tPHL|
1.5V
04604-019
tZH
O/P HIGH RxD 0V
tHZ
VOH 1.5V
04604-020
VOL
VOH -0.5V
Figure 13. Receiver Propagation Delay Figure 15. Receiver Enable/Disable Timing
Rev. PrK | Page 9 of 15
04604-021
ADM2485 TYPICAL PERFORMANCE CHARACTERISTICS
Preliminary Technical Data
Figure 16. Unloaded Supply Current vs. Temperature
Figure 19. Driver/Receiver Propagation Delay, Low to High (RLDiff = 54 , CL1 = CL2 = 100 pF)
Figure 20. Driver/Receiver Propagation Delay, High to Low (RLDiff = 54 , CL1 = CL2 = 100 pF) Figure 17. Driver Propagation Delay vs. Temperature
Figure 21. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per VDE 0884 Figure 18. Receiver Propagation Delay vs. Temperature
Rev. PrK | Page 10 of 15
Preliminary Technical Data
ADM2485
Figure 22. Output Current vs. Receiver Output High Voltage
Figure 25. Receiver Output Low Voltage vs. Temperature I = -4 mA
Figure 23. Output Current vs. Receiver Output Low Voltage
Figure 24. Receiver Output High Voltage vs. Temperature
I = -4 mA
Rev. PrK | Page 11 of 15
ADM2485 CIRCUIT DESCRIPTION
ELECTRICAL ISOLATION
In the ADM2485, electrical isolation is implemented on the logic side of the interface. Therefore, the part has two main sections: a digital isolation section and a transceiver section (see Figure 26). Driver input and data enable, applied to the TxD and RTS pins, respectively, and referenced to logic ground (GND1), are coupled across an isolation barrier to appear at the transceiver section referenced to isolated ground (GND2). Similarly, the receiver output, referenced to isolated ground in the transceiver section, is coupled across the isolation barrier to appear at the RxD pin referenced to logic ground.
Preliminary Technical Data
TRUTH TABLES
The truth tables in this section use these abbreviations:
Letter H I L X Z NC Description High level Indeterminate Low level Irrelevant High impedance (off) Disconnected
Table 6. Transmitting
iCoupler Technology
The digital signals are transmitted across the isolation barrier using iCoupler technology. This technique uses chip scale transformer windings to couple the digital signals magnetically from one side of the barrier to the other. Digital inputs are encoded into waveforms that are capable of exciting the primary transformer winding. At the secondary winding, the induced waveforms are then decoded into the binary value that was originally transmitted.
VDD1 ISOLATION BARRIER A TxD ENCODE DECODE D B VDD2
Supply Status VDD1 VDD2 On On On On On On On Off Off On Off Off
Inputs RTS H H L X X X
TxD H L X X X X
Output A B H L L H Z Z Z Z Z Z Z Z
DE OUT H H L L L L
Table 7. Receiving
Supply Status VDD1 VDD2 On On On On On On Off Off On On On On On Off On Off Inputs A-B (V) >0.2 <-0.2 -0.2 < A - B < 0.2 Inputs open X X X X
RE
L or NC L or NC L or NC L or NC H L or NC L or NC L or NC
Output RxD H L I H Z H H L
RTS
ENCODE
DECODE
DE OUT
RxD
DECODE
ENCODE
R
RE
DIGITAL ISOLATION
TRANSCEIVER
GND 1
GND 2
Figure 26. ADM2485 Digital Isolation and Transceiver Sections
Rev. PrK | Page 12 of 15
Preliminary Technical Data
THERMAL SHUTDOWN
MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kGAUSS) 100
ADM2485
The ADM2485 contains thermal shutdown circuitry that protects the part from excessive power dissipation during fault conditions. Shorting the driver outputs to a low impedance source can result in high driver currents. The thermal sensing circuitry detects the increase in die temperature under this condition and disables the driver outputs. This circuitry is designed to disable the driver outputs when a die temperature of 150C is reached. As the device cools, the drivers are re-enabled at a temperature of 140C.
10
1
0.1
0.01
The receiver input includes a fail-safe feature that guarantees a logic high RxD output when the A and B inputs are floating or open-circuited.
10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz)
100M
Figure 27. Maximum Allowable External Magnetic Flux Density
MAGNETIC FIELD IMMUNITY
Because iCouplers use a coreless technology, no magnetic components are present, and the problem of magnetic saturation of the core material does not exist. Therefore, iCouplers have essentially infinite dc field immunity. The analysis below defines the conditions under which this may occur. The ADM2485's 3 V operating condition is examined because it represents the most susceptible mode of operation. The limitation on the iCoupler's ac magnetic field immunity is set by the condition in which the induced error voltage in the receiving coil (the bottom coil in this case) is made sufficiently large, either to falsely set or reset the decoder. The voltage induced across the bottom coil is given by
- d 2 V = rn ; n = 1, 2, . . . , N dt
For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kGauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse and is the worst-case polarity, it reduces the received pulse from >1.0 V to 0.75 V--still well above the 0.5 V sensing threshold of the decoder. Figure 28 shows the magnetic flux density values in terms of more familiar quantities such as maximum allowable current flow at given distances away from the ADM2485 transformers.
1000 DISTANCE = 1m 100 DISTANCE = 5mm 10
where, if the pulses at the transformer output are greater than 1.0 V in amplitude: = magnetic flux density (gauss) N = number of turns in receiving coil rn = radius of nth turn in receiving coil (cm) The decoder has a sensing threshold of about 0.5 V; therefore, there is a 0.5 V margin in which induced voltages can be tolerated. Given the geometry of the receiving coil and an imposed requirement that the induced voltage is, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated, as shown in Figure 27.
MAXIMUM ALLOWABLE CURRENT (kA)
DISTANCE = 100mm 1
0.1
10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz)
100M
Figure 28. Maximum Allowable Current for Various Current-to-ADM2485 Spacings
At combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.
Rev. PrK | Page 13 of 15
04604-017
0.01 1k
04604-016
RECEIVER FAIL-SAFE INPUTS
0.001 1k
ADM2485 APPLICATIONS INFORMATION
PC BOARD LAYOUT
The ADM2485 isolated RS-485 transceiver requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure ). Bypass capacitors are most conveniently connected between Pin 3 and Pin 4 for VDD1 and between Pin 15 and Pin 16 for VDD2. The capacitor value should be between 0.01 F and 0.1 F. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should also be considered unless the ground pair on each package side is connected close to the package.
D1 D2 GND1 VDD1 RxD RE RTS TxD VDD2 GND2 GND2 B A GND2 DE OUT GND2
V CC 100nF VDD1 D1 D2
Preliminary Technical Data
output a regulated 5V output. If ADM2485 is powered by 5V on the logic side a 1CT:1.5CT transformer T1 is required so that therefore is enough headroom for the ADP667 LDO to output a regulated 5V output.
ISOLATION BARRIER 1N5817 IN V CC 22F OUT +5V 10F
ADP667
SET GND SHDN
T1
1N5817
ADM2485
ISO 5V 100nF V DD2
ADM2485
Figure 19. Recommended Printed Circuit Board Layout
GND 1 GND 2
In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isola tion barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins exceeding the device's absolute maximum ratings, thereby leading to latch-up or permanent damage.
Figure 20. Applications Diagram
APPLICATIONS DIAGRAM
The ADM2485 integrates a transformer driver which when used with an external transformer and LDO generates an isolated 5V power supply, to be supplied between the VDD2 and the GND2 pins. Pins D1 and D2 of the ADM2485 drive a center-tapped transformer T1, A pair of Schottky diodes and a smoothing capacitor are used to create a rectified signal from the secondary winding. The ADP667 linear voltage regulator provides a regulated 5V power supply to the ADM2485's busside circuitry (VDD2), as shown in Figure 20. When the ADM2485 is powered by 3V on the logic side a 1CT:2.2CT transformer T1 is required to step up the 3V to 6V, so that therefore is enough headroom for the ADP667 LDO to
Rev. PrK | Page 14 of 15
Preliminary Technical Data OUTLINE DIMENSIONS
10.50 (0.4134) 10.10 (0.3976)
ADM2485
16
9
7.60 (0.2992) 7.40 (0.2913)
1 8
10.65 (0.4193) 10.00 (0.3937)
1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122)
2.65 (0.1043) 2.35 (0.0925)
0.75 (0.0295) x 45 0.25 (0.0098)
SEATING PLANE
8 0.33 (0.0130) 0 0.20 (0.0079)
1.27 (0.0500) 0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 21. 16-Lead Wide-Body Small Outline Package [SOIC]
(RW-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model ADM2485BRWZ1 ADM2485BRWZ-REEL1 Data Rate (Mbps) 16 16 Temperature Range -40C to +85C -40C to +85C Package Description 16-Lead Wide Body SOIC 16-Lead Wide Body SOIC Package Option RW-16 RW-16
The addition of an "-RL" suffix designates a 13" (1000 units) tape and reel option.
1
Z = Pb-free part.
(c) 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06021-0-3/06(PrK)
Rev. PrK | Page 15 of 15

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